Method and apparatus for detecting and correcting anomalies in field-programmable gate arrays using CRCs for anomaly detection and parity for anomaly correction
US6101624A · kind A · utility
41Cited by
6References
13Claims
0Family size
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Key dates
| Filing date | Jul 20, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jul 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and means for detecting and correcting anomalies in a RAM-based FPGA by comparing CRC residues over portions of the RAM-stored connection bitmap with prestored residues derived from uncorrupted copies of the same bitmap portions. A mismatch selectively invokes either error reporting to the chip only, error reporting and immediate verification testing of counterpart FPGA chip functions, or error reporting, parity-based correction of the words in error, reprogramming of the chip functions with the corrected words, and verification testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.