Depletion mode MOS capacitor with patterned V.sub.T implants
US6103561A · kind A · utility
8Cited by
7References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 19, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Mar 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/03
Abstract
A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.