SiC patterning of porous silicon
US6103590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0445
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of selectively forming porous silicon regions (106) in a silicon substrate (100). A masking layer (104) of SiC is deposited by PECVD over the substrate (100) using an organosilicon precursor gas such as trimethylsilane, silane/methane, or tetramethylsilane at a temperature between 200-500.degree. C. The masking layer (104) of SiC is then patterned and etched to expose the region of the substrate (100) where porous silicon is desired. An anodization process is performed to convert a region of the substrate to porous silicon (106). The SiC masking layer (104) withstands the HF electrolyte of the anodization process with little to no degradation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.