Programmable logic device
US6104207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Apr 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. Fir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.