Sense amplifier control circuit in semiconductor memory
US6104656A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each other, successively. A first logic gate is supplied with a pair of sense amplifier enabling bar signals which are applied to the first logic gate in order. The first logic gate generates a signal of logic value 0 when at least one of the sense amplifier enabling bar signals has logic value 1. A second logic gate generates a first NMOS sense amplifier enabling bar signal of high level when an output of the first logic gate has logic value 0 and a sense amplifier enabling bar signal has logic value 1. A third logic gate generates a first PMOS sense amplifier enabling bar signal of high level when at least one of an output of the first logic gate and a sense amplifier enabling bar signal has logic value 1. A fourth logic gate generates a signal of logic value 1 when at least one of a plurality of MAT selection bar signals has logic value 0. A fifth logic gate generates a signal of logic value 1 when the first NMOS sense amplifier enabling bar signal has logic value 0 and an output of the fourth logic gate has logic value 1. A six…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.