Circuit and method for replacement of address translations
US6105110A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.