Method and apparatus for merging binary translated basic blocks of instructions
US6105124A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.