Method of making a circuit board having burr free castellated plated through holes
US6105246A · kind A · utility
1Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of creating a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation using conventional profiling methods, is removed or pre-profiled. The pre-profiled plated through hole is then profiled at a distance slightly off-set from the pre-profiled edge to further prevent burr formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.