Inventor · Port Crane, NY, US

James M. Larnerd

12Patents
4h-index
14Co-inventors
57Inventor score

Filing activity: Oct 6, 1987 → Jan 18, 2008

Most-cited inventions

PatentTitleAreaCited byStatus
US7348677B2 Method of providing printed circuit board with conductive holes and board resulting therefrom Electricity 14 Active
US7211289B2 Method of making multilayered printed circuit board with filled conductive holes Electricity 12 Expired
US4869418A Solder leveling method and apparatus Electricity 11 Expired
US4799616A Solder leveling method and apparatus Electricity 8 Expired
US7157646B2 Circuitized substrate with split conductive layer, method of making same, electrical assembly utilizing same, and information handling system utilizing same Emerging Cross-Sectional Technologies 4 Expired
US4979862A Automatic loading mechanism Electricity 3 Expired
US6105246A Method of making a circuit board having burr free castellated plated through holes Emerging Cross-Sectional Technologies 1 Expired
US7377033B2 Method of making circuitized substrate with split conductive layer and information handling system utilizing same Emerging Cross-Sectional Technologies 1 Active
US7157647B2 Circuitized substrate with filled isolation border, method of making same, electrical assembly utilizing same, and information handling system utilizing same Emerging Cross-Sectional Technologies 1 Expired
US6483046B1 Circuit board having burr free castellated plated through holes Emerging Cross-Sectional Technologies 1 Expired
US7814649B2 Method of making circuitized substrate with filled isolation border Emerging Cross-Sectional Technologies 0 Active
US7491896B2 Information handling system utilizing circuitized substrate with split conductive layer Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.