System and method for hardware emulation of a digital circuit
US6106565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A development system includes two processors which can each act as the central processing unit of the development system. Control is passed between the processors via a system management mode (SMM) interrupt under the X86 architecture. In one embodiment, one of the processor is a processor to be emulated and the other processor is an emulating processor. Since the emulating processor runs at a much slower clock speed than the emulated processor, an application program can be run by the emulating processor until a region of interest is reached. The control of the application program can then be transferred by the SMM interrupt to the emulated processor. This arrangement allows a new compatible microprocessor to be efficiently developed using a hardware emulation system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.