High performance DRAM structure employing multiple thickness gate oxide

US6107134A · kind A · utility

Assignee

• Etron Technology, Inc. · TW

Inventors

• Nicky C. Lu · Yorktown Heights, US
• Kun-Zen Chang · Hsinchu, TW

Key dates

• Filing date: Nov 1, 1999
• Grant date: Aug 22, 2000
• Expiry date: Nov 1, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.