Silylation method for reducing critical dimension loss and resist loss
US6107177A · kind A · utility
26Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing critical dimension loss and resist loss dimensions during etching includes providing a dielectric layer having an anti-reflection layer formed thereon and patterning a resist layer on the anti-reflection layer. The resist layer is exposed to an agent including silicon, and the agent is reacted with the resist to form a silylation region on exposed surfaces of the resist layer. The anti-reflection layer is etched by employing the silylation regions as an etch mask wherein the silylation regions have a greater resistance to etching than the antireflection layer and the resist layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.