Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6108240A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage V.sub.LOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage V.sub.ERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage V.sub.INT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage V.sub.INT applied to their gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.