Dynamic type semiconductor memory device
US6108264A · kind A · utility
21Cited by
23References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.