Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system
US6108737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.