Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits

US6108805A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Rochit Rajsuman · San Jose, US

Key dates

• Filing date: Oct 8, 1997
• Grant date: Aug 22, 2000
• Expiry date: Oct 8, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops. These Domino scan flip-flops can be used in the Domino logic as sequential elements to allow a multiplicity of logic functions to be implemented using Domino logic. These scan flip-flops can then be serially connected either as part of a separate scan chain or integrated i…