Using NO or N.sub.2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory
US6110780A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1999 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Apr 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A new method of using a NO or N.sub.2 O treatment on a first area on a wafer in order to form a thinner oxide film in the first area and a thicker oxide film in a second area on a wafer using a single oxidation step is achieved. A semiconductor substrate of a silicon wafer is provided wherein a first area is separated from a second area by an isolation region. The silicon substrate in the second area is treated with NO or N.sub.2 O whereby a high-nitrogen silicon oxide layer is formed on the surface of semiconductor substrate in the second area. A tunnel window is defined in the first area and the oxide layer within the tunnel window is removed. The silicon wafer is oxidized whereby a tunnel oxide layer forms within the tunnel window and whereby a gate oxide layer is formed overlying the high-nitrogen silicon oxide layer in the second area. The tunnel oxide layer has a greater thickness than the combined thickness of the gate oxide layer and the high-nitrogen silicon oxide layer. A conducting layer is deposited and patterned overlying the tunnel oxide layer and the gate oxide layer and fabrication of the integrated circuit device is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.