Method of mechanical polishing
US6110831A · kind A · utility
11Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, illustratively, having a dopant, dye, etc. termed a "marker layer" is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer is deposited upon the marker layer. The undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.