Very low power logic circuit family with enhanced noise immunity
US6111425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.