Low power multiplexer with shared, clocked transistor
US6111435A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.