High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle
US6112295A · kind A · utility
62Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.