Inventor · San Jose, CA, US

Kushagra Vaid

37Patents
9h-index
53Co-inventors
74Inventor score

Filing activity: Sep 24, 1998 → Oct 13, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US6598154B1 Precoding branch instructions to reduce branch-penalty in pipelined processors Physics 131 Expired
US6112295A High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle Physics 62 Expired
US7426648B2 Global and pseudo power state management for multiple processing elements Physics 17 Expired
US7984248B2 Transaction based shared data operations in a multiprocessor environment Physics 17 Expired
US8261266B2 Deploying a virtual machine having a virtual hardware configuration matching an improved hardware profile with respect to execution of an application Physics 16 Active
US7254676B2 Processor cache memory as RAM for execution of boot code Physics 14 Expired
US8533514B2 Power-capping based on UPS capacity Emerging Cross-Sectional Technologies 14 Active
US7721148B2 Method and apparatus for redirection of machine check interrupts in multithreaded systems Physics 10 Active
US8321630B1 Application-transparent hybridized caching for high-performance storage Physics 9 Active
US7587639B2 System and method for error injection using a flexible program interface field Physics 8 Active
US7849327B2 Technique to virtualize processor input/output resources Physics 8 Active
US8984265B2 Server active management technology (AMT) assisted secure boot Electricity 7 Active
US8161280B2 Launching a secure kernel in a multiprocessor system Physics 7 Active
US6684322B1 Method and system for instruction length decode Physics 6 Expired
US7770005B2 Launching a secure kernel in a multiprocessor system Physics 6 Active
US7213129B1 Method and system for a two stage pipelined instruction decode and alignment using previous instruction length Physics 6 Expired
US7360103B2 P-state feedback to operating system with hardware coordination Emerging Cross-Sectional Technologies 6 Expired
US9779249B2 Launching a secure kernel in a multiprocessor system Physics 5 Active
US8135723B2 Leveraging low-latency memory access Physics 4 Active
US7698552B2 Launching a secure kernel in a multiprocessor system Physics 4 Active
US8176266B2 Transaction based shared data operations in a multiprocessor environment Physics 3 Active
US7725713B2 Launching a secure kernel in a multiprocessor system Physics 3 Active
US7353433B2 Poisoned error signaling for proactive OS recovery Physics 2 Expired
US8458412B2 Transaction based shared data operations in a multiprocessor environment Physics 1 Active
US7774600B2 Launching a secure kernel in a multiprocessor system Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.