Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution
US6112297A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Feb 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.