Method of selecting layout of integrated circuit probe card
US6113646A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1997 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2851
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A probe card design method is described which optimizes the number of die probed per touchdown and minimizes the number of steps required to test an integrated circuit wafer. The method analyses rows of a wafer in sets. Assuming a specific probe card matrix, the number of touchdown steps required for each set is determined and a total number of touchdown steps required for the wafer is determined. This method is repeated for a plurality of probe card matrixes. The size of the first set can be varied to determine an optimum offset which reduces the number of touchdown steps required to test the wafer. Each set is analyzed by dividing the longest row of the set by the width of the probe card matrix and rounding a result up to the nearest integer. The result of each set is summarized to indicate a minimum number of touchdowns required to test a wafer. A probe card matrix design can be selected based upon the minimum number of touchdowns, number of test sites in a probe card matrix, and a physical size of the matrixes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.