Method of fabricating metal-oxide semiconductor transistor
US6114196A · kind A · utility
2Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1999 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOS transistor. An undoped multi-layer stacked polysilicon structure is formed on a gate oxide layer and then being doped to increase conductivity. After that, the multi-layer stacked polysilicon structure and the gate oxide layer are patterned to form a gate electrode. A source/drain region is formed by ion implantation with the gate electrode as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.