Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6114201A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jun 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a multiple fin-shape capacitor with a plurality of horizontal fins and vertical pillars. First, a contact hole formed on a semiconductor substrate using an etching process. A first polysilicon layer is then deposited in the contact hole to form a plug. A composition layer consists of BPSG and silicon oxide formed on the substrate. Then a opening is formed in the composition layer to serve as a storage node. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed along the surface of the composition layer, the substrate and the plug. Then a SOG layer is formed along the surface of the second polysilicon layer. A CMP process is used to polish a portion of the SOG layer and a portion of the second polysilicon layer on the top of the composition layer. The SOG layer and the composition layer are subsequently removed by BOE solution. A dielectric film is then formed o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.