Method and apparatus for interconnecting multiple circuit chips
US6114221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an interconnected multiple circuit chip structure by etching a first substrate to form protrusions on its surface. Then the protrusions are preferentially etched to produce a selected shape such as a tetragonal protrusion and an integrated circuit is then fabricated on the substrate. A second substrate is preferentially etched to form recesses having a selected shape that is the complement of the selected shape of the protrusions of the first substrate and then an integrated circuit is fabricated on the second substrate. The protrusions and recesses are coated with an electrically conductive metal such as aluminum. The first and second substrates are joined and aligned together such that the protrusions mate with the recesses and the structure is annealed such that the metal coatings thereon come into contact to electrically connect the integrated circuits on the substrates. The method can also be used to electrically connect multiple chips mounted back to front.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.