Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region

US6115233A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• John J. Seliskar · Charlottesville, US
• Derryl D. J. Allman · Camas, US
• John Gregory · Greenbrier, US
• James P. Yakura · Colorado Springs, US
• Dim-Lee Kwong · Austin, US

Key dates

• Filing date: Jun 28, 1996
• Grant date: Sep 5, 2000
• Expiry date: Jun 28, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.