John J. Seliskar
15Patents
10h-index
7Co-inventors
61Inventor score
Filing activity: Jun 28, 1996 → Mar 19, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5985705A | Low threshold voltage MOS transistor and method of manufacture | Electricity | 129 | Expired |
| US7211864B2 | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | Electricity | 112 | Expired |
| US6355532B1 | Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET | Electricity | 70 | Expired |
| US6115233A | Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region | Electricity | 51 | Expired |
| US6316817A | MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor | Emerging Cross-Sectional Technologies | 37 | Expired |
| US5858828A | Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor | Emerging Cross-Sectional Technologies | 37 | Expired |
| US7714384B2 | Castellated gate MOSFET device capable of fully-depleted operation | Electricity | 32 | Active |
| US6284586A | Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking | Electricity | 19 | Expired |
| US7968409B2 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof | Electricity | 16 | Active |
| US6525377B1 | Low threshold voltage MOS transistor and method of manufacture | Electricity | 13 | Expired |
| US7719058B2 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof | Electricity | 10 | Active |
| US8138544B2 | Castellated gate MOSFET tetrode capable of fully-depleted operation | Electricity | 10 | Active |
| US7439139B2 | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | Electricity | 9 | Active |
| US5780329A | Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask | Emerging Cross-Sectional Technologies | 6 | Expired |
| US8664071B2 | Castellated gate MOSFET tetrode capable of fully-depleted operation | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.