Dynamic RAM having word line voltage intermittently boosted in synchronism with an external clock signal
US6115319A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.