Clock skew management method and apparatus
US6115827A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an integrated circuit having core logic with two or more clock domains and at least one signal path originating in one clock domain and terminating in an other clock domain, each signal path having a source control element in the one clock domain and an associated destination control element in the other clock domain, each the control element being a scannable memory element, the method comprising the steps of, for each the control element shifting a test stimulus into all scannable elements in the core logic; placing an associated source control element in a hold mode for a predetermined number of clock cycles prior to a capture operation so that the source control element holds its output constant during the predetermined number of clock cycles; performing a capture operation for capturing the data output in response to the test stimulus by the control element and by all other scannable elements which are not control elements; maintaining an associated source control element in a hold mode for a predetermined number of clock cycles following a capture operation so that the source control element holds its output constant during the predetermined number of cloc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.