Silicon carbide vertical FET and method for manufacturing the same
US6117735A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are positioned relative to each other, with respect to the first mask. If a mask including a tapered end portion is used, and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region may be formed by self-alignment, using only one mask. By controlling the impurity concentration of the channel region, the threshold voltage can be controlled, and a normally-off type FET can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.