Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package
US6117759A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jan 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process. The method includes the steps of providing a semiconductor device having at least one first interconnect structure connected to a surface of the semiconductor device (501), and a substrate having a plurality of metallized pads (503); placing an at least one second interconnect structure in aligned contact with one or more of the plurality of metallized pads (505); placing the at least one first interconnect structure in aligned contact with one or more of the plurality of metallized pads (507); and simultaneously reflowing the at least one first interconnect structure and the at least one second interconnect structure such that the semiconductor device and at least one second interconnect structure are connected to the metallized pads of the substrate (509).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.