Semiconductor device and manufacturing method thereof
US6118145A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Jun 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A semiconductor device with a reduced slope between components, and a method of manufacturing a semiconductor device, represented by DRAM, having a large difference of level between components, for planarizing an inter-layer insulating film covering respective components in accordance with a design to precisely reduce a slope of the inter-layer insulating film over the difference in level between components, without increasing the number of manufacturing steps or introducing complicated manufacturing steps. Each storage node electrode connected to a source is formed, and an electrically isolated dummy pattern is simultaneously formed on an inter-layer insulating film. Then, a BPSG film is formed and reflowed, followed by etching back the surface of the BPSG film. Subsequently, the dummy pattern is used as an index for indicating the end of the etch back, and the BPSG film is etched back until a portion of a cell plate electrode covering the dummy pattern is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.