Semiconductor die metal layout for flip chip packaging
US6118180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.