Method and apparatus for logic synchronization
US6118304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal. The present invention additionally provides that a logic gate may only feed another logic circuit in a feed back loop or a feed forward loop that uses the next phase clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.