INTRINSITY, INC.
69Patents
0Active
69Granted
32Portfolio score
Filing activity: Feb 5, 1998 → Dec 16, 2003
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7219326B2 | Physical realization of dynamic logic using parameterized tile partitioning | Physics | 192 | Expired |
| US6260131A | Method and apparatus for TLB memory ordering | Physics | 105 | Expired |
| US6457170B1 | Software system build method and apparatus that supports multiple users in a software development environment | Physics | 57 | Expired |
| US6272653A | Method and apparatus for built-in self-test of logic circuitry | Physics | 49 | Expired |
| US6370632B1 | Method and apparatus that enforces a regional memory model in hierarchical memory systems | Physics | 37 | Expired |
| US6301600A | Method and apparatus for dynamic partitionable saturating adder/subtractor | Physics | 36 | Expired |
| US6567835B1 | Method and apparatus for a 5:2 carry-save-adder (CSA) | Physics | 34 | Expired |
| US6275838A | Method and apparatus for an enhanced floating point unit with graphics and integer capabilities | Physics | 34 | Expired |
| US6438743B1 | Method and apparatus for object cache registration and maintenance in a networked software development environment | Physics | 34 | Expired |
| US6107835A | Method and apparatus for a logic circuit with constant power consumption | Physics | 26 | Expired |
| US6898691B2 | Rearranging data between vector and matrix forms in a SIMD matrix processor | Physics | 25 | Expired |
| US6211456A | Method and apparatus for routing 1 of 4 signals | Physics | 23 | Expired |
| US6288589A | Method and apparatus for generating clock signals | Physics | 18 | Expired |
| US6118304A | Method and apparatus for logic synchronization | Physics | 18 | Expired |
| US6275841A | 1-of-4 multiplier | Physics | 18 | Expired |
| US6209076A | Method and apparatus for two-stage address generation | Physics | 17 | Expired |
| US6367065B1 | Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation | Physics | 17 | Expired |
| US6460134B1 | Method and apparatus for a late pipeline enhanced floating point unit | Physics | 16 | Expired |
| US6622240B1 | Method and apparatus for pre-branch instruction | Physics | 16 | Expired |
| US6345381B1 | Method and apparatus for a logic circuit design tool | Physics | 14 | Expired |
| US6181596A | Method and apparatus for a RAM circuit having N-Nary output interface | Physics | 13 | Expired |
| US6557021B1 | Rounding anticipator for floating point operations | Physics | 13 | Expired |
| US6604065B1 | Multiple-state simulation for non-binary logic | Physics | 12 | Expired |
| US6202194A | Method and apparatus for routing 1 of N signals | Physics | 12 | Expired |
| US6271683A | Dynamic logic scan gate method and apparatus | Physics | 11 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.