Changing clock frequency
US6118306A · kind A · utility
103Cited by
6References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.