Circuit assembly and method of synchronizing plural circuits
US6118314A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Oct 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.