Ferroelectric memory device and method for driving it
US6118688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device having a memory cell internally provided with first and second ferroelectric capacitors, with first and second memory cell transistors interposed between first and second bit lines (BL, /BL) and the data accumulation nodes (SN, /SN) of the first and second ferroelectric capacitors, respectively, and with a cell plate line (CP) connected to the cell plate of each of the first and second ferroelectric capacitors is controlled by the following procedures. After L data is written in the memory cell capacitor during the period between times t12 and t13, H data is written in the memory cell capacitor by control operation during the period between the time t13 and a time t14. At the time t14, the voltage on a word line (WL) is switched to L to turn OFF the first memory cell transistor, while the writing of H data in the first ferroelectric capacitor is continued by using residual charge. A high-speed write operation is accomplished by increasing the amount of charge retained by the ferroelectric memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.