Patent · US Expired

Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability

US6118689A · kind A · utility

20Cited by
2References
1Claims
0Family size

Inventors

Key dates

Filing dateOct 27, 1999
Grant dateSep 12, 2000
Priority date—
Expiry dateOct 27, 2019

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C8/16
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

This invention reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With an unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.