Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU
US6119141A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | May 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The function selection signal of an ALU is resistively decoupled or serially coupled to the input multiplexers of the ALU. By producing delayed function selection signals and decoupling the delayed function signals from the input multiplexers, the input multiplexers are serially activated. This need not impact the overall speed of the ALUs, since the adders are also serially activated by virtue of the carry signal ripple. However, by resistively decoupling the function selection signal from the input multiplexers, the load seen by the input driver that drives the function selection signal inputs of the multiplexer may be reduced, thereby allowing the least significant bit input multiplexer to be activated more rapidly. Moreover, resistive decoupling may be implemented by polysilicon resistors, thereby allowing metal interconnect layers in the integrated circuit to be used for other purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.