Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system
US6119203A · kind A · utility
85Cited by
4References
14Claims
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Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10) provides a mechanism for choosing when the data stream touch (DST) controller (300) is allowed access to the data cache and MMU (50). The mechanism uses a count value to determine at what point in program execution the DST controller (300) is allowed to interrupt normal load and store accesses. This allows DST prefetches to be optimized for maximum performance of the data processing system (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.