Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
US6121086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
In a DRAM, a plurality of memory cells each consisting of a memory cell selection transistor Qs and an information storage capacity element connected thereto in series are provided on a semiconductor substrate 1. An active region of the memory cell selection MISFET Qs is formed to have an isolated rectangular plan view. A part of the bit line BL extends in a direction crossing the extending direction thereof, and the extending part two-dimensionally overlaps a semiconductor region formed in the active region and is electrically connected thereto. In the DRAM having this structure, the bit line BL is formed of conductive films 16b1 and 16b2 embedded in the contact hole 14b for the bit line and in the wiring groove 15a for the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.