Method for manufacturing gallium nitride compound semiconductor
US6121121A · kind A · utility
160Cited by
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3Claims
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Key dates
| Filing date | Jul 27, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Jul 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An Al.sub.0.15 Ga.sub.0.85 N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows epitaxially and three-dimensionally (not only in a vertical direction but also in a lateral direction) on the Al.sub.0.15 Ga.sub.0.85 N layer 2. Since the GaN layer grows epitaxially in the lateral direction as well, a GaN compound semiconductor having a greatly reduced number of dislocations is obtained in lateral growth regions (regions A where the substrate 1 is exposed).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.