Semiconductor device trench isolation structure with polysilicon bias voltage contact

US6121148A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Rashid Bashir · Champaign, US
• Wipawan Yindeepol · San Jose, US

Key dates

• Filing date: Jan 26, 1999
• Grant date: Sep 19, 2000
• Expiry date: Jan 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76286
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device, polysilicon-contacted trench isolation structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and make…