Split gate oxide asymmetric MOS devices
US6121666A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
Abstract
A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either the source or drain that is thinner than the remainder of the gate oxide. The thin "notched" region of gate oxide lies over a region of the device's channel region that has been engineered to have a relatively "high" threshold voltage (near 0 volts) in comparison to the remainder of the channel region. This region of higher threshold voltage may be created by a pocket region of increased dopant concentration abutting the source or the drain (but not both) and proximate the channel region. The pocket region has the opposite conductivity type as the source and drain. A device so structured behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket region is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET. If the pocket region is located under the drain, the reverse arrangement will be true. The region of thin gate oxide (the notched region) provides a higher gate capacitance than the remaining region…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.