Executing partial-width packed data instructions
US6122725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30196
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.