Technique for ordering internal processor register accesses
US6122728A · kind A · utility
6Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register instructions are identified with register groups indicating which processor registers are affected by the execution of the register instruction. The progress of the execution of the register instruction is then controlled depending upon the identified register groups, in order to avoid conflicts with other concurrently processed instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.