Burn in technique for chips containing different types of IC circuitry
US6122760A · kind A · utility
11Cited by
24References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Aug 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2856
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An improved technique for testing semi-conductor chips having different types of circuits thereof is provided. The burn-in test includes providing test engines and/or externally applied patterns for each of the different types of circuits, stressing at high temperature and increased voltage, the semi-conductor containing both types of circuits, and running a sequence of patterns on each of said types of circuits simultaneously by the use of the engines for at least one of the types of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.